1. Field of the Invention
The present invention relates to circuits for generating specified voltage levels. More particularly, this invention pertains to an improved bias network for providing ECL reference voltages.
2. Background of the Invention
Emitter-coupled logic (ECL) circuits comprise a very useful family of digital integrated circuits. ECL originated long before the invention of integrated circuits. The IC process has permitted the development of such circuits so that ECL is currently the fastest commercially available form of digital IC with typical propagation delay times of less than 1 ns and clock rates approaching 1 GHz.
ECL circuits are based upon the non-saturating current switch, also known as the emitter-coupled pair. By careful choice of circuit parameters (including supply current) the basic ECL circuit can be designed so that the bipolar transistors in the current switch do not saturate, contributing to the short propagation delay time typical of ECL circuits.
BiCMOS chips with ECL I/O's generally operate between ground and a supply voltage of approximately -5 volts, requiring a reference voltage v.sub.1 of approximately -1.3 volts. In the event that full ECL stages are also implemented, an additional reference voltage v.sub.2 about 1.2 volts above the supply voltage (V.sub.ss) is required.
The reference voltages should be maintained as independent as possible of both temperature and supply voltage to maintain stable logic reference voltage and output voltage levels. Unfortunately, both of these critical values are affected by temperature and supply voltage. The shifting of the voltage transfer characteristic introduces design problems that are particularly acute in large digital systems that incorporate many smaller units, each subjected to a separate supply voltage and ambient temperature.
Conventionally, attempts to obtain temperature independent biasing have followed a number of approaches. In one approach, a Zener diode reference is employed, requiring large voltages. As an alternative, a band-gap reference can be employed that combines a voltage having a negative temperature coefficient (e.g. a base-emitter voltage) with one having a positive temperature coefficient (i.e., voltage proportional to the thermal voltage V.sub.T =kT/q where k=Boltzmann constant, T=temperature, q=electron charge). A bias network of the latter type is disclosed in FIG. 1.
While some success has been experienced in overcoming temperature effects, efforts to counteract supply voltage irregularities have been less successful in the prior art. A common method for compensating such variations has been the addition of a shunt transistor that acts as a regulator, holding the collector current of a transistor of the voltage generator constant. Unfortunately, such arrangement requires the use of a pnp transistor as the shunt element. As a result, the fabrication of an adequate device is significantly complicated by the inherently lateral geometry of pnp devices (npn transistors, on the other hand are vertical geometry devices). The fabrication of vertical pnp devices can be quite difficult and costly. Furthermore, it is well recognized that pnp transistors are significantly slower than npn devices.